Quote Originally Posted by kur4o View Post
I have another theory. The chip has built in rom with $800 bytes and some bootloader. At reset the $800 bytes are copied to ram and the loop is executed from there. Later eside can take control and rewrite the $800 bytes with user specified code. In 94-95 the code is what the pcm needs, so it is not updated. In 96-97 the code needs some changes and eside loads new custom code for the new features of the pcm.

The TPU might have different memory layout and the shared memory there can be seen at $0-$2df compared to eside 1400-16df.

I looked again at the data and it seems like 8byte instruction scheme. Each 8 bytes represent some instructions sequence and the second byte is likely 00 or randomly around 80 or 40.

It could be some form of calibration data.

I agree with you, and I think we shouldn't consider the TPU as a microprocessor, I'm pretty sure it's an FPGA matrix with a tiny bootloader, like in 68332 micros. The binary opcodes for 68332 TPU are really dense in data packing (i.e. only two MSb define the major operation, the rest are operands), so there might be no obvious repetition in 16 or 8 bits looking at the binary.