That explanation is awesome. Finally managed to figure some of the free flowing timers on both sides that were meaningless till now. The code flow also makes sense now.
The prescale is 16 on 94-95 code, which equals to 12.5ms.

Is it possible that tside runs on different frequency. I made some calculations but could`nt get it right. I might be missing something there. The engine run time counter there is known to increase each second but I managed to calculate a 0.8seconds increment. Which doesn`t look correct.

SO there isn`t any queued interrupts on hc11.

I found some code that re enables the SCSSI or set it to default on 5 second inactivity on the bus.

Code:
clr     byte_1886
bclr    byte_37 $42 ; 'B'
ldaa    #$26 ; '&'
staa    SCCR2           ; SCI Control Register
ldx     #$1803
bclr    0,x 4
sei
ldaa    PORTD           ; Port D Data
anda    #$ED ; 'ý'
oraa    #$2C ; ','
staa    PORTD           ; Port D Data
cli
ldd     #0
std     word_1882
std     word_1880
I might change the location of it to enable it on the beginning of the oc4i and keep the bus quiet on the irq execution. I also have to disable all the chatter on the bus to keep the processor happy. And keep it disabled on the higher rpms.

By looking of the size of the irq, can you estimate the time the processor needs to execute it.
Did you managed to crack the aldl and obd communication. Is the data written to external chip that manages the rest or the processor handles the timing and so on. I wonder how the scssi interrupt is invoked.