Quote Originally Posted by kur4o View Post
Tom H

The explanation says it all. So if you read the full flash chip the empty regions will be 0-1fff and 10000-17fff.

I have some routines that will erase and write the intel chips. You can set it up for the bootstrap mode and try some flashing.

Maybe we can move the conversation to the 96-97 lt1 thread.
Yes, that's what I expect. The question of if the gate is AND or NAND does come into this though and would just flip the banks. Easy to sort out if I had a working Tside (I don't at the moment). One issue gives me pause with what I wrote... the DLC interrupt seems to be in the switched bank. In the case this interrupt fires in the upper bank, the PCM will crash. Yipes did I find a bug???? or is that interrupt just not used. If not used, why provide a vector in a switched bank.

I am getting closer to being able to help with this but still struggling with some of the basics. Also struggling with finger problems... I soldered a header strip in place of the flex cable that broke. I should have placed one on the comp side to use a standard ribbon cable. now I need to cross all the wires ^&%&^%&^%

When I get the latest little (?) project of the schematic done, I would like to disassemble the erase and write routines. Have you already done this??

-Tom