A short summary of Motorola 68HC11 assembly commands, compiled by TheGreatJ. Abbr. Machine code Action summary ABA 1B Add acc. B to acc. A ABX 4A Add acc. B (unsigned) to reg. X ABY 18-3A Add acc. B (unsigned) to reg. Y ADCA 89,99,A9,B9 Add target to acc. A with carry flag ADCB C9,D9,E9,F9 Add target to acc. B with carry flag ADDA 8A,9A,AA,BA Add target to acc. A without carry flag ADDB CA,DA,EA,FA Add target to acc. B without carry flag ADDD C4,D4,E4,F4 Add 16-bit target to double acc. ^ ANDA 85,95,A5,B5 Perform logic AND with acc. A and target ANDB C5,D5,E5,F5 Perform logic AND with acc. B and target ASLA 48 Shift acc. A one bit left, clear b0, set carry bit if b7 was previously set (effectively multiplies target by 2) ASLB 58 Shift acc. B one bit left, clear b0, set carry bit if b7 was previously set (effectively multiplies target by 2) ASL 68,78,18-68 Shift target one bit left, clear b0, set carry bit if b7 was previously set (effectively multiplies target by 2) ASLD 05 Shift double acc. one bit left, clear b0, set carry bit if b7 was previously set (effectively multiplies target by 2) ^ ASRA 47 Shift acc. A one bit right , hold b7 constant, clear carry bit ASRB 57 Shift acc. B one bit right, hold b7 constant, clear carry bit ASR 67,77 Shift target value one bit right, hold b7 constant, clear carry bit BCC 24 Branch to address if carry flag clear BCLR 15,18-2D Clear specified bits at target BCS 25 Branch to address if carry flag set BEQ 27 Branch to address if zero flag set BGE 2C Branch to address if target was greater than or equal to acc. (zero flag clear, and, negative flag and overflow flag both set or both clear) BHI 22 Branch to address if target had greater magnitude than acc. (carry flag clear and zero flag clear) BHS 24 Branch to address if target had equal or greater magnitude than acc. (carry flag clear) BITA 86,96,A6,B6 Perform logic AND between acc. A and target, set zero/negative flag accordingly BITB C6,D6,E6,F6 Perform logic AND between acc. B and target, set zero/negative flag accordingly BLE 2F Branch to address if target was less than or equal to acc. (zero flag set, OR, negative flag XOR overflow flag set) BLO 25 Branch to address if target had equal or less magnitude than acc. (carry flag set) BLS 23 Branch to address if target had less magnitude than acc. (carry flag OR zero flag is set) BLT 2D Branch to address if taget was less than acc. (negative flag XOR overflow flag set) BMI 2B Branch to address if negative flag set BNE 26 Branch to address if zero flag clear BPL 2A Branch to address if negative flag is clear BRA 20 Branch to address BRCLR 13,18-2F Branch to address if specified bits of target are clear BRN 21 Do not branch (simple 3-cycle delay) BRSET 12,18-2E Branch to address if specified bits of target are set BSET 14,18-2C Set specified bits at target, leave other bits unchanged BSR 8D Branch to subroutine, save return address to stack (LSB first) BVC 28 Branch to address if overflow flag clear BVS 29 Branch to address if overflow flag set CBA 11 Compare acc. A to acc. B and set condition flags accordingly CLC 0C Clear carry flag CLI 0E Clear interrupt flag (enable interrupts) CLRA 4F Clear all bits in acc. A CLRB 5F Clear all bits in acc. B CLR 6F,7F,18-6F Clear all btis at target CLV 0A Clear overflow flag CMPA 81,91,A1,B1,18-A1 Subtract target from acc. A and set condition flags accordingly CMPB C1,D1,E1,F1,18-E1 Subtract target from acc. B and set condition flags accordingly COMA 43 Replace contents of acc. A with it's complement COMB 53 Replace contents of acc. B with it's complement COM 63,73,18-63 Replace contents of target with it's one's complement CPD 1A-(83,93,A3,B3),CD-A3 Compare 16-bit target to double acc. and set condition flags accordingly ^ CPX 8C,9C,AC,BC,CD-AC Compare 16-bit target to reg. X and set condition flags accordingly CPY 18-(8C,9C,AC,BC),1A-AC Compare 16-bit target to reg. Y and set condition flags accordingly DAA 19 Correct condition flags after an add command (ABA,ADD,ADC) involving binary-coded decimal values DECA 4A Subtract one from acc. A DECB 5A Subtract one from acc. B DEC 6A,7A,18-6A Subtract one from target DES 34 Subtract one from stack pointer DEX 09 Subtract one from reg. X DEY 18-09 Subtract one from reg. Y EORA 88,98,A8,B8,18-A8 Perform logic Exclusive-OR between target and acc. A and store result in acc. A EORB C8,D8,E8,F8,18-E8 Perform logic Exclusive-OR between target and acc. B and store result in acc. B FDIV 03 Divide double acc. by reg. X and place quotient in reg. X and remainder in double acc. (assumes quotient less than one) and set condition flags accordingly IDIV 02 Divide double acc. by reg. X and place quotient in reg. X and remainder in double acc. (assumes quotient greater than one) and set condition flags accordingly INCA 4C Add one to acc. A INCB 5C Add one to acc. B INC 6C,7C,18-6C Add one to target INS 31 Add one to stack pointer INX 08 Add one to reg. X INY 18-08 Add one to reg. Y JMP 6E,7E,18-6E Jump to address JSR 9D,AD,BD,18-AD Store program counter to stack, LSB first, then jump to address LDAA 86,96,A6,B6,18-A6 Load target to acc. A LDAB C6,D6,E6,F6,18-E6 Load target to acc. B LDD CC,DC,EC,FC,18-EC Load 16-bit target to double acc. ^ LDS 9E,AE,BE,EE,18-AE Load 16-bit target to stack pointer, MSB first LDX CE,DE,EE,FE,CD-EE Load 16-bit target to reg. X LDY 18-(CE,DE,EE,FE),1A-EE Load 16-bit target to reg. Y LSLA Same as ASLA LSLB Same as ASLB LSL Same as ASL LSLD Same as ASLD LSRA 44 Shift acc. A one bit right, clear b7, set carry flag if b0 was previously set LSRB 54 Shift acc. B one bit right, clear b7, set carry flag if b0 was previously set LSR 64,74,18-64 Shift target value one bit right, clear b7, set carry flag if b0 was previously set LSRD 04 Shift double acc. one bit right, clear b15, set carry flag if b0 was previously set ^ MUL 3D Multiply acc. A by acc. B and store result in double acc. ^ NEGA 40 Replace acc. A with it's two's complement NEGB 50 Replace acc. B with it's two's complement NEG 60,70,18-60 Replace target value with it's two's complement NOP 01 No operation (simple 2-cycle delay) ORAA 8A,9A,AA,BA,18-AA Perform logic Inclusive-OR between acc. A and target and store result in acc. A ORAB CA,DA,EA,FA,18-EA Perform logic Inclusive-OR between acc. B and target and store result in acc. B PSHA 36 Store acc. A to stack PSHB 37 Store acc. B to stack PSHX 3C Store reg. X to stack, LSB first PSHY 18-3C Store reg. Y to stack, LSB first PULA 32 Load acc. A from stack PULB 33 Load acc. B from stack PULX 38 Load reg. X from stack, MSB first PULY 18-38 Load reg. Y from stack, MSB first ROLA 49 Shift acc. A one bit left, set carry flag if b7 was previously set, set b0 if carry flag was previously set ROLB 59 Shift acc. B one bit left, set carry flag if b7 was previously set, set b0 if carry flag was previously set ROL 69,79,18-69 Shift target one bit left, set carry flag if b7 was previously set, set b0 if carry flag was previously set RORA 46 Shift acc. A one bit right, set carry flag if b0 was previously set, set b7 if carry flag was previously set RORB 56 Shift acc. B one bit right, set carry flag if b0 was previously set, set b7 if carry flag was previously set ROR 66,76,18-66 Shift target one bit right, set carry flag if b0 was previously set, set b7 if carry flag was previously set RTI 3B Load condition flags, acc. B, acc. A, reg. X (MSB first,) reg. Y (MSB first,) and program counter (MSB first) from stack in that order RTS 39 Load program counter from stack, MSB first SBA 10 Subtract acc. B from acc. A and place result in acc. A SBCA 82,92,A2,B2,18-A2 Subtract (with carry flag) target from acc. A and place result in acc. A SBCB C2,D2,E2,F2,18-E2 Subtract (with carry flag) target from acc. B and place result in acc. B SEC 0D Set carry flag SEI 0F Set interrupt flag SEV 0B Set overflow flag STAA 97,A7,B7,18-A7 Store acc. A to target STAB D7,E7,F7,18-E7 Store acc. B to target STD DD,ED,FD,18-ED Store double acc. to 16-bit target, MSB first STOP CF Stop processing and system clocks, unless prevent stop flag set (if prevent stop flag set, treat as NOP) STS 9F,AF,BF,18-AF Store stack pointer to 16-bit target, MSB first STX DF,EF,FF,CD-EF Store reg. X to 16-bit target, MSB first STY 18-(DF,EF,FF),1A-EF Store reg. Y to 16-bit target, MSB first SUBA 80,90,A0,B0,18-A0 Subtract target from acc. A and place result in acc. A SUBB C0,D0,E0,F0,18-E0 Subtract target from acc. B and place result in acc. B SUBD 83,93,A3,B3,18-A3 Subtract 16-bit target from double acc. and place result in double acc. SWI 3F Store program counter, reg. X, reg. Y, acc. A, acc. B, and conditionf flags to stack; set interrupt flag, load 16-bit target to program counter TAB 16 Copy acc. A to acc. B (contents of acc. B are lost) TAP 06 Copy acc. A to condition flags (can clear but not set X interrupt flag) * TBA 17 Copy acc. B to acc. A (contents of acc. A are lost) TEST 00 Continuously incrememnt program counter (valid only while MPU in test mode) TPA 07 Copy condition flags to acc. A * TSTA 4D Subtract $00 from acc. A and set condition flags accordingly TSTB 5D Subtract $00 from acc. B and set condition flags accordingly TST 6D,7D,18-6D Subtract $00 from target and set condition flags accordingly TSX 30 Load address of last stacked value to reg. X TSY 18-30 Load address of last stacked value to reg. Y TXS 35 Load stack pointer with reg. X minus one (address in reg. X will point to last value on stack) TYS 18-35 Load stack pointer with reg. Y minus one (address in reg. Y will point to last value on stack) WAI 3E Store program counter (LSB first,) reg. Y (LSB first,) reg. X (LSB first,) acc. A, acc. B, and condition flags to stack; wait for interrupt XGDX 8F Exchange double acc. with reg. X XGDY 18-8F Exchange double acc. with reg. Y Machine code is in Hex. Multiple command variations are seperated by commas. Dashes indicate 2-byte commands. ^ double accumulator: acc. A=MSB and acc. B=LSB, allows direct use of 16-bit values and mathematics * condition flags: b7=prevent stop, b6=X interrupt, b5=half carry, b4=interrupt, b3=negative, b2=zero, b1=overflow, b0=carry